1. Field of the Invention
The present invention relates to an apparatus for performing a timing analysis of a circuit in designing a semiconductor integrated circuit and a program thereof.
2. Description of the Related Art
A static timing analysis (STA), used in conventional semiconductor integrated circuit designing, verifies whether a circuit operates or not within a range between the maximum and the minimum delay values with variations, employing delay average value μ and standard deviation σ of a gate circuit, as shown in FIG. 1A. For example, in a case of a 3σ model, the timing verification is performed with in a range of the maximum value μ+3σ and the minimum value μ−3σ. However, it is rare that only one gate circuit is present in an actual circuit, and therefore, timing verification in a case that a plurality of gate circuits are combined is required.
In the conventional STA, as shown in FIG. 1B, a delay variation margin (also referred to as the standard deviation herein) of a circuit with a line of a plurality of gates is used for calculation of a standard deviation of a whole circuit, employing the standard deviations σ1, σ2, σ3, σ4 . . . of each gate circuit (element), by the following equation.σ=σ1+σ2+σ3+σ4+ . . .   (1)
Suppose the standard deviations of all the elements are equal, for example, delay of n number of the elements is σ=nσ1.
In the recent statistical STA, calculation of a standard deviation as the whole circuit by the following equation is also being examined (see Patent Document 1 below, for example).σ=√{square root over (σ12+σ22+σ42+σ42+ . . . )}  (2)Patent Document 1:Japanese Patent Published Application No. 2003-316849
For example, when the standard deviations of all the elements are equal, the delay of n elements can be represented by the following equation.σ=√{square root over (n)}σ1  (3)
However, the above conventional timing analysis has the following problems.
In the timing verification in circuit designing, the variations of a plurality of the elements are simplified; however, the actual variations are not so simple as the variations in timing verification. For example, there is a correlation such that when the delay of an element A is larger than the average value, the delay of an element B is likely to be larger as well. For that reason, the timing verification based on the estimation of the simplified variations, may cause an excess margin or an inadequate margin of the timing, incurring waste of motion or blocking circuit operation.
In the timing verification with the correlation, in general, using a correlation coefficient rAB between the element A and the element B, a term rABσAσB gives a contribution to a variance. Therefore, the variance of a circuit comprising elements A, B, C and others can be expressed by the following equation.σ2=σA2+σB2+ . . . +2rABσAσB+2rACσAσC+2rBCσBσC+ . . .   (4)
The same variance as expressed above is used in the case of timing verification of a circuit comprising cells A, B, C and others, regarding a cell comprising one or more elements as a single circuit element. However, in recent years, types of cells employed for circuit designing are of great variety, and therefore the combinations of the cells become an enormous number. Therefore, experimentally examining the correlation of all the combinations, or calculating the correlation of a number of paths by a computer involves a great deal of time, and it is not realistic. In addition, it is more important to improve efficiency and performance in semiconductor manufacture rather than to achieve mathematical accuracy.